Tải bản đầy đủ

kiến trúc máy tính dạng thanh tin figs 5 the instruction set architecture level sinhvienzone com

5
THE INSTRUCTION SET
ARCHITECTURE LEVEL

1

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


FORTRAN 90
program

C program

FORTRAN 90
program compiled
to ISA program

C program

compiled
to ISA program
Software

ISA level
Hardware
ISA program executed
by microprogram or hardware

Hardware

Figure 5-1. The ISA level is the interface between the compilers and the hardware.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


Address

Address

8 Bytes

15

14

13

12

11

8 Bytes

10

9


8

24
16
8
0

19
15

14

13

17

16

12

Aligned 8-byte
word at address 8
(a)

18

Nonaligned 8-byte
word at address 12
(b)

Figure 5-2. An 8-byte word in a little-endian memory. (a)
Aligned. (b) Not aligned. Some machines require that words in
memory be aligned.

CuuDuongThanCong.com

24
16
8
0

https://fb.com/tailieudientucntt


Bits

16

8
AH
BH
CH
DH

8
A X
B X
C X
D X

AL

EAX

BL

EBX

CL

ECX

DL

EDX

ESI
EDI
EBP
ESP

CS
SS
DS
ES
FS
GS

EIP

EFLAGS

Figure 5-3. The Pentium II’s primary registers.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


Register
R0
R1 – R7
R8 – R13
R14
R15
R16 – R23
R24 – R29
R30
R31

Alt. name
G0
G1 – G7
O0 – O5
SP
O7
L0 – L7
I0 – I5
FP
I7

Function
Hardwired to 0. Stores into it are just ignored.
Holds global variables
Holds parameters to the procedure being called
Stack pointer
Scratch register
Holds local variables for the current procedure
Holds incoming parameters
Pointer to the base of the current stack frame
Holds return address for the current procedure

Figure 5-4. The UltraSPARC II’s general registers.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


R0
R1

G0
G1

0
Global 1

G0
G1

Global 7

R7

G7

R8

O0

0
Global 1






G7





R7

R0
R1

Global 7

CWP = 6




Alternative name

R13
R14
R15

O5
SP
O7

Stack pointer
Temporary

R16

L0

Local 0





CWP = 7
R8

O0

Outgoing parmeter 0

Local 7

R24

I0

Incoming parameter 0

Outgoing parmeter 5
Stack pointer
Temporary

R16

L0

Local 0





R23

L7

Local 7

R24

10

Incoming parameter 0



Incoming parmeter 5
Frame pointer
Return address
(a)

Overlap

R29
R30
R31

CWP
decremented
on call in
this direction

I5
FP
I7



OS
SP
O7

I5
FP
I7

L7






R13
R14
R15

R29
R30
R31

R23

Incoming parmeter 5
Frame pointer
Return address

Part of
previous window

Part of
previous window

(b)

Figure 5-5. Operation of the UltraSPARC II register windows.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


Type
Signed integer
Unsigned integer
Binary coded decimal integer
Floating point

8 Bits
×
×
×

16 Bits
×
×

32 Bits
×
×

64 Bits

×

×

Figure 5-6. The Pentium II numeric data types. Supported
types are marked with ×.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt

128 Bits


Type
Signed integer
Unsigned integer
Binary coded decimal integer
Floating point

8 Bits
×
×

16 Bits
×
×

32 Bits
×
×

64 Bits
×
×

128 Bits

×

×

×

Figure 5-7. The UltraSPARC II numeric data types.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


Type
Signed integer
Unsigned integer
Binary coded decimal integer
Floating point

8 Bits
×

16 Bits
×

32 Bits
×

64 Bits
×

×

×

Figure 5-8. The JVM numeric data types.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt

128 Bits


OPCODE
(a)

OPCODE

ADDRESS1 ADDRESS2
(c)

OPCODE

ADDRESS
(b)

OPCODE ADDR1 ADDR2 ADDR3
(d)

Figure 5-9. Four common instruction formats: (a) Zeroaddress instruction. (b) One-address instruction (c) Twoaddress instruction. (d) Three-address instruction.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


1 Word

1 Word

Instruction

Instruction

Instruction

Instruction

Instruction

Instruction

Instruction

Instruction

Instruction

Instruction

Instruction

Instruction

(a)

(b)

1 Word
Instruction
Instruction

Instr.

Instruction
(c)

Figure 5-10. Some possible relationships between instruction
and word length.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt

Instr.


15

14

13

Opcode

12

11

10

Address 1

9

8

7

6

5

Address 2

4

3

2

Address 3

Figure 5-11. An instruction with a 4-bit opcode and three 4-bit
address fields.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt

1


16 bits
4-bit
opcode

0000 xxxx yyyy zzzz
0001 xxxx yyyy zzzz
0010 xxxx yyyy zzzz

15 3-address
instructions


1100 xxxx yyyy zzzz
1101 xxxx yyyy zzzz
1110 xxxx yyyy zzzz
8-bit
opcode

1111 0000 yyyy zzzz
1111 0001 yyyy zzzz
1111 0010 yyyy zzzz

14 2-address
instructions


1111 1011 yyyy zzzz
1111 1100 yyyy zzzz
1111 1101 yyyy zzzz
12-bit
opcode

1111 1110 0000 zzzz
1111 1110 0001 zzzz

31 1-address
instructions


1111
1111
1111
1111

1110
1110
1111
1111

1110
1111
0000
0001

zzzz
zzzz
zzzz
zzzz


1111 1111 1101 zzzz
1111 1111 1110 zzzz
16-bit
opcode

1111 1111 1111 0000
1111 1111 1111 0001
1111 1111 1111 0010

16 0-address
instructions


1111 1111 1111 1101
1111 1111 1111 1110
1111 1111 1111 1111
15 12 11 8 7 4 3 0
Bit number

Figure 5-12. An expanding opcode allowing 15 three-address
instructions, 14 two-address instructions, 31 one-address instructions, and 16 zero-address instructions. The fields marked
xxxx, yyyy, and zzzz are 4-bit address fields.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


Bytes

Bits

0-5

1-2

0-1

0-1

0-4

0-4

PREFIX

OPCODE

MODE

SIB

DISPLACMENT

IMMEDIATE

6

1 1

Bits

INSTRUCTION

2

3

3

SCALE

INDEX

BASE

Which operand is source?
Byte/word
Bits

2

3

3

MOD

REC

R/M

Figure 5-13. The Pentium II instruction formats.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


Format
1a

2

1b

5

6

5

1

8

5

DEST

OPCODE

SRC1

0

FP-OP

SRC2

DEST

OPCODE

SRC1

1

5

3

22

DEST

OP

IMMEDIATE CONSTANT

3

22

OP

PC-RELATIVE DISPLACEMENT

2
2
2
3

IMMEDIATE CONSTANT

1

4

A COND

3 Register
Immediate

SETHI

BRANCH

30

2

PC-RELATIVE DISPLACEMENT

4

CALL

Figure 5-14. The original SPARC instruction formats.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


Bits

8

8

8

8

8

Format
1

OPCODE

2

OPCODE

3

OPCODE

4

OPCODE

5

OPCODE

INDEX

DIMENSIONS

6

OPCODE

INDEX

#PARAMETERS

7

OPCODE

INDEX

8

OPCODE

32-BIT BRANCH OFFSET

9

OPCODE

VARIABLE LENGTH…

BYTE

BYTE = index, constant or type

SHORT

INDEX

SHORT = index, constant or offset

CONST

0

CONST

Figure 5-15. The JVM instruction formats.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


MOV

R1

4

Figure 5-16. An immediate instruction for loading 4 into register 1.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


MOV R1,#0 ; accumulate the sum in R1, initially 0
MOV R2,#A ; R2 = address of the array A
MOV R3,#A+1024; R3 = address if the first word beyond A
LOOP:
ADD R1,(R2); register indirect through R2 to get operand
ADD R2,#4
; increment R2 by one word (4 bytes)
CMP R2,R3 ; are we done yet?
BLT LOOP
; if R2 < R3, we are not done, so continue
Figure 5-17. A generic assembly program for computing the
sum of the elements of an array.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


MOV R1,#0 ; accumulate the OR in R1, initially 0
MOV R2,#0 ; R2 = index, i, of current product: A[i] AND B[i]
MOV R3,#4096; R3 = first index value not to use
LOOP:
MOV R4,A(R2); R4 = A[i]
AND R4,B(R2) ; R4 = A[i] AND B[i]
OR R1,R4
; OR all the Boolean products into R1
ADD R2,#4
; i = i + 4 (step in units of 1 word = 4 bytes)
CMP R2,R3 ; are we done yet?
BLT LOOP
; if R2 < R3, we are not done, so continue
Figure 5-18. A generic assembly program for computing the
OR of Ai AND Bi for two 1024-element arrays.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


MOV

R4

R2

124300

Figure 5-19. A possible representation of MOV R4,A(R2) .

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


A

California

x

(

B

+

C

)

New York
Switch

Texas


Figure 5-20. Each railroad car represents one symbol in the
formula to be converted from infix to reverse Polish notation.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt




Most recently arrived car
on the Texas line



Car at the switch
+ – x
/
(

)



4

1

1

1

1

1

5

+

2

2

2

1

1

1

2



2

2

2

1

1

1

2

x

2

2

2

2

2

1

2

/

2

2

2

2

2

1

2

(

5

1

1

1

1

1

3

Figure 5-21. Decision table used by the infix-to-reverse Polish
notation algorithm

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


Infix
A+B×C
A×B+C
A×B+C×D
(A + B) / (C − D)
A×B/C
((A + B) × C + D)/(E + F + G)

Reverse Polish notation
ABC×+
AB×C+
AB×CD×+
AB+CD−/
AB×C/
AB+C×D+EF+G+/

Figure 5-22. Some examples of infix expressions and their reverse Polish notation equivalents.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


Step
1
2
3
4
5
6
7
8
9
10
11
12
13

Remaining string
825×+132×+4−/
25×+132×+4−/
5×+132×+4−/
×+132×+4−/
+132×+4−/
132×+4−/
32×+4−/
2×+4−/
×+4−/
+4−/
4−/
−/
/

Instruction
BIPUSH 8
BIPUSH 2
BIPUSH 5
IMUL
IADD
BIPUSH 1
BIPUSH 3
BIPUSH 2
IMUL
IADD
BIPUSH 4
ISUB
IDIV

Stack
8
8, 2
8, 2, 5
8, 10
18
18, 1
18, 1, 3
18, 1, 3, 2
18, 1, 6
18, 7
18, 7, 4
18, 3
6

Figure 5-23. Use of a stack to evaluate a reverse Polish notation formula.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


Bits

8

1

5

5

5

1

OPCODE

0

DEST

SRC1

SRC2

2

OPCODE

1

DEST

SRC1

3

OPCODE

8

OFFSET

OFFSET

Figure 5-24. A simple design for the instruction formats of a
three-address machine.

CuuDuongThanCong.com

https://fb.com/tailieudientucntt


Tài liệu bạn tìm kiếm đã sẵn sàng tải về

Tải bản đầy đủ ngay

×